SEMICONDUCTOR MEMORY

摘要

PURPOSE: To provide a semiconductor storage device in which the occurrence of data destruction due to the erroneous start of a refresh operation is prevented even when noise is superimposed on a low address strobe signal. CONSTITUTION: A refresh operation is started is started in response to the activation of a refresh control signal ZCBR. A refresh control circuit 110 controls the activation of a refresh control signal ZCBR under the consideration of the signal level of not only control signals CAS and RASF activated according to the activation of a /CAS signal and a /RASF signal necessary for the recognition of CBR refresh start but also a low address decode enable signal RADE being an inside control signal which is activated according to the activation of the /RAS signal and maintains the active state until the /RAS signal is be activated.