PHASE LOCKED LOOP CIRCUIT MAINTAINING FREQUENCY DEFLECTION

摘要

PURPOSE: A phase locked loop circuit is provided to block an external reference clock signal so as to output an internally generated frequency signal in the case where the reference clock signal is beyond a tolerable error range. CONSTITUTION: A reference clock error detector(60) outputs an error detection signal when the variation of a frequency is beyond a tolerable deflection reference, and a multiplexer(70) outputs either one of two input signals in response to a signal from the reference clock error detector(60). A phase detector(50) detects a phase difference between the reference clock signal and a signal from a divider(100), and a low pass filter(80) filters an output signal of the multiplexer(70). A voltage controlled oscillator(90) outputs a frequency signal of a high stability as a frequency corresponding to a voltage signal from the low pass filter(80). The divider(100) divides the frequency signal from the voltage controlled oscillator(90) so as to become the same frequency as the reference clock signal.