| 摘要 |
PURPOSE: An isolation method of a semiconductor device is provided to reduce a 3-dimensional gate induced leakage current and parasitic capacitance, by preventing a gate oxide layer from being thinly formed or by preventing etching residue of a gate. CONSTITUTION: An isolation region and an active region are defined in a semiconductor substrate(20). An etching mask is formed on the semiconductor substrate. A predetermined depth of the isolation region of the substrate is removed to form a trench by using the etching mask. An insulating layer is formed on the entire substrate to fill the trench. A chemical mechanical polishing(CMP) process is performed to make the insulating layer remain only in the trench region by using the etching mask as a stop layer. The etching mask is eliminated to expose the surface of the substrate. The substrate including the remaining insulating layer is cleaned. An insulating material layer(240) of which fluidity is superior is formed on the substrate including the remaining insulating layer. An anisotropic etching is performed regarding the insulating material layer to planarize the surface of the insulating layer and the surface of the substrate by using the surface of the substrate as an etching mask.
|
