发明名称 |
Staggering execution of an instruction by dividing a full-width macro instruction into at least two partial-width micro instructions |
摘要 |
A method and apparatus are disclosed for staggering execution of an instruction. According to one embodiment of the invention, a single macro instruction is received wherein the single macro instruction specifies at least two logical registers and wherein the two logical registers respectively store a first and second packed data operands having corresponding data elements. An operation specified by the single macro instruction is then performed independently on a first and second plurality of the corresponding data elements from said first and second packed data operands at different times using the same circuit to independently generate a first and second plurality of resulting data elements. The first and second plurality of resulting data elements are stored in a single logical register as a third packed data operand.
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申请公布号 |
US6233671(B1) |
申请公布日期 |
2001.05.15 |
申请号 |
US19980052825 |
申请日期 |
1998.03.31 |
申请人 |
INTEL CORPORATION |
发明人 |
ABDALLAH MOHAMMAD;COKE JAMES S.;FISCHER STEVE;PENTKOVSKI VLADMIR |
分类号 |
G06F9/30;G06F9/302;G06F9/315;G06F9/318;G06F9/38;(IPC1-7):G06F7/38 |
主分类号 |
G06F9/30 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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