| 摘要 |
PURPOSE: A chip debugging circuit is provided to easily search chip errors during a process of developing the chips, and to develop a debugger for debugging an application embedded on the completed chips. CONSTITUTION: The circuit comprises a controller(100), a plurality of test data registers(300-1,2,3), and a clock generator(200). The controller(100) outputs control signals(HOLD, sel) and test clock signals(tck_1,2,3) based on an external control signal(CTL) and clock signal(TCK), and at the same time outputs a scan enable signal(SE) based on clock signals(fclk2, fclk3) from the clock generator(200). The test data registers(300-1,2,3) store test data(SIN), scans the test data(SIN) according to the scan enable signal(SE), and output the scanned test data in synchronization with clock signals(CLK1,2,3) from the clock generator(200). The clock generator(200) receives a system clock(sysCLK), and outputs the clock signals(fclk2, fclk3) for the controller(100) and the drive clocks(CLK1,2,3) for the test data registers(300-1,2,3) based on the system clock(sysCLK).
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