| 摘要 |
A single large register increments ticks of a high-speed clock. A single compare register is associated with the clock register, the compare register preferably being of equivalent length to the clock register. Successive previously-stored timing values are then loaded into the compare register. Typically the timing values are pre-sorted in chronological order. A comparator monitors the clock register's current value and compares it with the timing value currently loaded in the compare register. As the clock register's value reaches the current timing value in the compare register, an alert signal is generated and sent out to activate a particular timed operation identified by an event ID ("EID") associated with the timing value in the compare register. The current timing value in the compare register is then discarded, and the next timing value in sequence is retrieved into the compare register. In a first embodiment, timing values are stored in a hardware stack. These values then "roll down" into the compare register as the clock register reaches successive timing values. In a second embodiment, the stack is configured in extensible memory. A third embodiment of the invention uses non-linear memory storage techniques, such as those used with a linked list, to generate the sequence of timing values that will be successively loaded into the compare register.
|
