| 摘要 |
PURPOSE: To reduce inter-cycle jitters in a clock generator, to which an EMI countermeasures are subjected. CONSTITUTION: In a secondary PLL having a loop filter 7 constituted of a first capacity and a first resistance, the decrease in comparison frequencies can be suppressed by using a clock-modulating circuit 2 controlled by a signal 16 obtained by frequency-dividing the oscillation signal of a voltage-controlled oscillator 13 for recursively controlling a frequency-divider 15, and the generation of a high-frequency noise can be minimized, by using a primary ΔΣ modulator 21 to the clock-modulating circuit 2, and a system can be obtained as a third-order PLL, by using a second capacity 3 having a capacitative value which is not less than 1/10 times as large as that of the first capacity in parallel with the loop filter 7. Thus, inter-cycle jitters can be suppressed by effectively removing the high-frequency noise.
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