| 摘要 |
PURPOSE: A method for manufacturing a self-aligned contact hole of a semiconductor device is provided to guarantee overlay margin regarding a plug poly by forming a cell array contact of a slope shape, and to reduce ohmic contact resistance by forming a peripheral circuit contact of a vertical shape. CONSTITUTION: A semiconductor substrate(11) is prepared which has a gate electrode and a source/drain region. The gate electrode has a spacer(16) and a hard mask layer. The source/drain region is formed at both sides of the gate electrode. A plug poly(18) is formed in spaces at both sides of the gate electrode spacer to be in contact with the source/drain region. An interlayer dielectric(19) is formed on the resultant structure having the plug poly. The interlayer dielectric is dry-etched by using a recipe having a slope characteristic to expose the plug poly in contact with the drain region. The interlayer dielectric is dry-etched by using a recipe having a vertical characteristic on the resultant structure so that a contact in a peripheral circuit portion is etched to the silicon substrate.
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