发明名称 |
Multiple-mode clock distribution apparatus and method with adaptive skew compensation |
摘要 |
An apparatus and method for distributing a clock signal within circuitry disposed on a number of separate system cards includes a first system card that generates a reference clock signal representative of a fixed delay of a system clock signal. A number of variable clock signals are produced using the system clock signal. Each of a number of system cards separate from the first system card receive one of the variable clock signals. A delay associated with the reference clock signal is typically longer than a delay associated with each of the variable clock signals. The phase of each of the variable clock signals is adjusted to a substantially in-phase relationship with respect to the reference clock signal in response to a phase difference between the reference clock signal an output signal received from each of the separate system cards. Producing each of the variable clock signals may involve selecting between a first delay line and a second delay line, and then producing the variable delay signal using the selected first or second delay line. A delay factor of the non-selected first or second delay line may be changed by varying a resistance and a current of one or more delay elements of the non-selected first or second delay lines. The circuitry is selectably operable in a slave or buffer-type clock repowering mode or an adaptive mode. The variable clock signals and the output signals may respectively comprise low voltage differential signals (LVDS) or CMOS level signals.
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申请公布号 |
US6232806(B1) |
申请公布日期 |
2001.05.15 |
申请号 |
US19980177142 |
申请日期 |
1998.10.21 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
WOESTE DANA MARIE;STROM JAMES DAVID;RUDOLPH BRUCE GEORGE |
分类号 |
G06F1/10;H03K5/13;H03L7/07;H03L7/081;(IPC1-7):H03K7/06 |
主分类号 |
G06F1/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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