METHOD FOR PLANARIZING SEMICONDUCTOR DEVICE

摘要

PURPOSE: A method for planarizing a semiconductor device is provided to prevent a reverse step coverage phenomenon by performing a planarizing process using a CMP process after applying a polishing stop layer of a PE-TEOS(Plasma Enhanced-Tetra Ethyl Ortho Silicate) to a step coverage portion between a cell portion and a peripheral circuit portion . CONSTITUTION: A BPSG(Boron Phosphorus Silicate Glass) layer(16) is formed on a semiconductor substrate(12) comprising a cell portion and a peripheral circuit portion. A PE-TEOS layer is formed on the BPSG layer. The resultant structure is planarized by a CMP process, wherein after exposing the BPSG layer of the cell portion, a polishing speed at the peripheral circuit portion having a low step coverage is reduced due to a PE-TEOS layer, thereby polishing uniformly the cell portion and the peripheral circuit portion. The BPSG layer is deposited in the thickness of 8000-30000Å. The PE-TEOS layer have 1/3-1/5 of a polishing selectivity with regard to the BPSG layer.