METHOD FOR FABRICATING INTEGRATED CIRCUIT USING HETERO-JUNCTION BIPOLAR TRANSISTOR

摘要

PURPOSE: A method for fabricating an integrated circuit using a hetero-junction bipolar transistor is provided to reduce a chip size by forming an resistant epitaxial layer in an epitaxial structure. CONSTITUTION: An epitaxial resistance layer(22) is formed on a semi-insulating compound semiconductor substrate(21). A sub-collector layer(23), a collector layer(24), a base layer(25), an emitter cap layer(27) are formed on the epitaxial resistance layer(22). An emitter metal layer(28) is deposited thereon. An emitter(26) connected with the emitter electrode(28) is formed by etching selectively the emitter cap layer(27) and the emitter layer(26). A base electrode(29) is formed on a selected portion of the exposed base layer(25). A base(25) is formed by etching the base layer(25) and the collector layer(24). A collector(24) is formed by etching the sub-collector layer(23). An electrode(30) is formed on a selected portion of the collector(24). A resistance electrode(31) is formed on a selected portion of the exposed epitaxial layer(22). A high resistance body(31) is formed by etching a part of the epitaxial resistance layer(22) and a part of the semi-insulating compound semiconductor substrate(21). A NiCr layer and a NoCr contact metal are deposited thereon. A low resistance body(34) is formed by etching selectively the NoCr contact metal.