发明名称 CLOCK CHANGEOVER METHOD
摘要 <p>PROBLEM TO BE SOLVED: To provide a clock changeover method for a system where a node device whose clock source is interrupted continues its operation, by which occurrence of a bit error can be eliminated due to presence of two clocks, which are a clock of a clock source and an internal clock of the node device on the occurrence of a fault in the transmission line or the node device, are basically designed identical to each other but unattainable of their equality and increase the difference as time elapses. SOLUTION: In the case of switching a communication path on the occurrence of fault of the transmission line or the node device, the clock is switched synchronously therewith. Thus, occurrence of the difference of the clocks is not caused and the effect given onto user data can be minimized.</p>
申请公布号 JP2001127773(A) 申请公布日期 2001.05.11
申请号 JP19990308227 申请日期 1999.10.29
申请人 TOSHIBA CORP 发明人 WATANABE HIROYUKI;TSUJI KIYOTAKA
分类号 H04L1/22;H04L7/00;H04L12/28;(IPC1-7):H04L12/28 主分类号 H04L1/22
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