METHOD FOR VERIFYING LAYOUT PATTERN AND BACK ANNOTATION SYSTEM

摘要

PROBLEM TO BE SOLVED: To solve a problem that much time is required up to the start of timing verification in a circle delay after the end of arrangement/wiring because the execution of LVS and the collation of a net list with a layout pattern are required for delay calculation. SOLUTION: In the semiconductor integrated circuit layout pattern verification method for collating a net list 1 with a net list 2 including a parasitic element extracted from a layout pattern, a net list 3 is prepared by removing the parasitic element from the net list 2 and the net list 1 is collated with the net list 3 to judge whether the layout pattern is prepared on the basis of the net list 1 or not.