| 摘要 |
PROBLEM TO BE SOLVED: To provide a layout method of a semiconductor integrated circuit for reducing influences of a cross talk. SOLUTION: A minimum interval is made so as to pass only one wiring therebetween, and power supply (VDD, VSS) wirings at a minimum line width are disposed in a vertical axial direction in n layers and in a horizontal axial direction in (n+1) layers to form a lattice-like shield, which is wired with a signal line. Furthermore, when (n-1) layers and (n+2) layers are used in a multilayer wiring of three layers or more, the power supply wiring is disposed in the signal line of the (n+1) layer, to shield vertically. Incidentally, a wiring may be made in the (n+1) and (n-1) layers in the vertical direction and in the n and (n+1) layers in the horizontal direction.
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