发明名称 MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE
摘要 PROBLEM TO BE SOLVED: To realize a semiconductor device which reduces an inter-wiring capacitance, and which is hard to generate a short-circuit failure between adjacent wirings or a connection failure of the wiring to an interlayer connecting metal plug, if misalignment occurs. SOLUTION: A first metal layer 103 for a first wiring and a second metal layer 104 for forming an interlayer connecting metal plug are deposited on an insulation film 2, and they are etched by using the same first resist as a mask, to form a shape of the first wiring, by using a second resist as a mask, only the second metal layer 104 is etched to form the interlayer connecting metal plug, whereby the interlayer connecting metal plug is reliably formed on the first wiring. Next, an interlayer insulation film 108 is formed so as to form porosities 107 relative to the first metal layer 103 as the first wiring, and the surface is flattened to form a second wiring connected to a plug composed of the second metal layer 104.
申请公布号 JP2001127154(A) 申请公布日期 2001.05.11
申请号 JP19990306439 申请日期 1999.10.28
申请人 MATSUSHITA ELECTRONICS INDUSTRY CORP 发明人 HIRANO HIROSHIGE;UEDA TETSUYA
分类号 H01L23/522;H01L21/768;(IPC1-7):H01L21/768 主分类号 H01L23/522
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