SYNCHRONIZING CIRCUIT

摘要

PROBLEM TO BE SOLVED: To solve the problem that it is difficult to constitute a synchronizing circuit while increasing in the occupation area and power consumption of a semiconductor integrated circuit are suppressed. SOLUTION: A variable delay line 12 outputs a clock signal whose phase is advanced by a time corresponding to the sum tH+tL of a time tH needed to output high-level data from an OCD circuit 18 and a time tL needed to output low-level data. A replica circuit 15 has the same constitution with a circuit that the low-level data of the OCD circuit 18 passes through and outputs a start signal SSL for outputting the high-level data from the OCD circuit 18. A replica circuit 17 has the same constitution with a circuit that the high-level data of the OCD circuit 18 passes through.