发明名称 SCRAMBLER CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a parallel system scrambler circuit having functions for coping with change of an operational function, correcting a bit error occurrence due to a failure and generating a pseudo error by realizing the diversification of a relational expression. SOLUTION: This scrambler circuit is provided with an n-bit matrix operation circuit 10 receiving an n-bit (n is an integer of >=2) input signal A, and an n-bit register circuit 20 receiving the n-bit signal outputted form the n-bit matrix operation circuit 10 and outputting an n-bit output signal B. The n-bit matrix operation circuit 10 is arranged for a control circuit 11 including at least either an exclusive OR gate XORx taking an exclusive OR of the n-bit input signal A and the n-bit output signal or an excusive OR gate XORx taking an exclusive OR of both output signals. To the control signal 11, an input of the exclusive OR gate XORx can be changed on the basis of an external m-bit (m is an integer, of >=2 control signal C), and thus, the diversification of the relational expression can be realized in a parallel system scrambler circuit.
申请公布号 JP2001125483(A) 申请公布日期 2001.05.11
申请号 JP19990301802 申请日期 1999.10.25
申请人 NEC CORP 发明人 NAKAMURA YASUSHI
分类号 G09C1/00;H04L9/18;(IPC1-7):G09C1/00 主分类号 G09C1/00
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