| 摘要 |
<p>A processor architecture comprises a program counter for executing M independent program streams on an instruction basis in timesharing manner, an N-stage pipeline shared by the program streams and operable at a frequency F, and a unit for executing the only S program streams in accordance with the operation performance required. The processor architecture are built up of M processors having an operating frequency of F/M connected in parallel, where M and N are mutually dependent integers that are equal to or greater than 1, S is an integer that is equal to or greater than 0 and satisfies S≤M, and N/M is the number of stages viewed from each program stream.</p> |
