| 摘要 |
Non-power-of-two grey-code counters (AP1, AP4, AP5, AP6), including modulos-10, 12, 14, and 22 are disclosed, along with a sequencing method they employ. Each counter includes a register (REG, 402, 502, 602) for storing an N-bit, e.g., 4-bit, grey-code count. The count is converted to binary code by a grey-to-binary-code translator (GBT, 403, 503, 603). The resulting binary count is incremented by an N-bit incrementer (BIN, 404, 504, 604) that skips certain binary values by toggling least-significant bits in unison when indicated by certain most-significant binary bits. The result is converted to grey-code by a binary-to-grey-code translator (BGT, 401, 501, 601). The translated result is stored in the register as the next count. An algorithm (M2) is disclosed for designing such a grey-code counter for any even modulo. The modulo is expressed as a sum of positive and negative terms, each term being a power of two. The exponents of the terms determine the counter design.
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