| 摘要 |
<p>A method for analyzing failures for semiconductor memories, in a ccordance with the present invention, includes providing a memory device including at least one memory chip. The at least one memory chip includes a redundancy calculation region (210). The at least one memory chip is tested to determine failure addresses (Fail-Addresses) of failed components on each memory chip. The addresses of the failed components are input to the redundancy calculation region to compare the failure addresses to previous failure addresses (X[a] and/or Y[a]) stored in the redundancy calculation region (in memory 200) to determine if new failures have been discovered. If a match exists between the previous failure addresses and the failure addresses, the failure addresses which match are terminated. Otherwise, the failure addresses are stored in the redundancy calculation region (in memory 200). It is then determined if the at least one memory chip is fixable based on the new failures which have been discovered.</p> |
