发明名称 Process for producing multilayer wiring boards
摘要 An improved process for producing a multilayer wiring board that has a plurality of conductor patterns and an interlevel dielectric layer on at least one surface of a substrate, with via holes or trench-like channels being provided at specified sites of said interlevel dielectric layer to establish an electrical interconnection between said conductor patterns, wherein prior to the provision of said via holes or trench-like channels, a coating having resistance to sandblasting is formed in a pattern over the interlevel dielectric layer and then sandblasting is performed to remove the interlevel dielectric layer in selected areas to form the via holes or trench-like channels and, thereafter, the coating having resistance to sandblasting is removed, followed by the provision of a conductive layer.
申请公布号 US6228465(B1) 申请公布日期 2001.05.08
申请号 US19990273265 申请日期 1999.03.22
申请人 TOKYO OHKA KOGYO CO., LTD. 发明人 TAKIGUCHI YOSHIKAZU;OBIYA HIROYUKI;TAKAHASHI TORU;SHIROYAMA TAISUKE;TAZAWA KENJI
分类号 H05K3/00;H05K3/46;(IPC1-7):B32B3/00 主分类号 H05K3/00
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