发明名称 |
Finite field multiplier with intrinsic modular reduction |
摘要 |
A finite field multiplier with intrinsic modular reduction includes an interface unit (1208) that translates an n bit wide data path to a m bit wide data path where n is less than m. Also included is a finite field data unit (1204) with m bit wide registers that is coupled to a finte field control unit (1202). The finite field control unit (1202) includes a microsequencer (1402) and a finite state machine multiplier (1404). The microsequencer (1402) controls the finite state machine multiplier (1404) which performs a finite field multiply operation with intrinsic modular reduction and presents a finite field multiplication product to the finite field data unit (1204).
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申请公布号 |
US6230179(B1) |
申请公布日期 |
2001.05.08 |
申请号 |
US19970997960 |
申请日期 |
1997.12.24 |
申请人 |
MOTOROLA, INC.;CERTICOM CORP. |
发明人 |
DWORKIN JAMES DOUGLAS;TORLA MICHAEL JOHN;GLASER P. MICHAEL;VADEKAR ASHOK;LAMBERT ROBERT JOHN;VANSTONE SCOTT ALEXANDER |
分类号 |
G06F7/72;G06F9/302;G09C1/00;(IPC1-7):G06F7/00 |
主分类号 |
G06F7/72 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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