发明名称 Method of manufacturing semiconductor devices with alleviated electric field concentration at gate edge portions
摘要 With the present invention, in a memory cell of a stacked-gate NOR flash EEPROM, for example, a SiON film is selectively formed on the sidewalls of a floating gate electrode and the top surface and sidewalls of a control gate electrode. Thereafter, annealing is done in an oxidative atmosphere, thereby carrying out a post-oxidation process. This allows an oxide film to grow gradually at the gate edge portions contacting a tunnel oxide film or interlayer insulating film of the floating gate electrode and control gate electrode. The formation of the SiON film on at least on the sidewalls of the floating gate electrode prevents oxidation at those portions. On the other hand, the gate edge portions of the floating gate electrode eventually become round. By improving the shape of the gate edge portions of the floating gate electrode in this way, an electric field is prevented from concentrating at the gate edge portions of the floating gate electrode.
申请公布号 US6228717(B1) 申请公布日期 2001.05.08
申请号 US19980196002 申请日期 1998.11.19
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 HAZAMA HIROAKI;AMEMIYA KAZUMI;WATANABE TOSHIHARU
分类号 H01L21/8247;H01L21/28;H01L27/115;H01L29/423;H01L29/51;H01L29/78;H01L29/788;H01L29/792;(IPC1-7):H01K21/824 主分类号 H01L21/8247
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