Transparent extended state save

摘要

A microprocessor having a standard register set and an extended register set, which is configured to save its state upon suspension of either an extended register process or a standard register processor. The microprocessor is configured to execute both standard register instruction sequences and extended register instruction sequences. A first memory is provided for storing a state of the microprocessor when a standard register instruction set sequence is suspended. The microprocessor further comprises a second memory for storing a microprocessor state upon suspension of the microprocessor executing an extended register instruction set sequence. An extended state save circuit coupled between a microprocessor core and the second memory allows the extended state of the microprocessor to be stored without modification of the operating system. As a result, the extended state of the microprocessor can be saved transparently to the operating system.