| 摘要 |
A high-density programmable logic device is presented, comprising two or more logic built-in blocks interconnected by a programmable global interconnect multiplex matrix. Each logic built-in block contains four groups of four macrocells and four I/O cells, two sub AND arrays and four sub OR arrays. Each sub OR array couples a group of macrocells, and each sub AND array drives two sub OR arrays. The sub AND and OR arrays can either function independently or be connected together by AND array or OR array connection facilities, to extend the logic capability. Every macrocell can be flexibly controlled by three levels of control signal: global, logic built-in block wide or separate. The outputs from the macrocells and the inputs from I/O cells can be fed locally back through the local feedback path, and also fed globally to other logic built-in blocks, through the global interconnect multiplex matrix. The interconnections in the global interconnect multiplex matrix are in an exclusive mode, such that only the feedbacks from other logic built-in blocks can be routed into a certain logic built-in block. All the global feedbacks are fed to the multiplexers in a specific pattern that maximizes the routeability of a selected global feedback to a selected logic built-in block input, while maintaining high speed and using less chip array.
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