| 摘要 |
A data processing system, circuit arrangement, integrated circuit device, program product, and method utilize a unique prefetch circuit arrangement that speculatively fetches instructions for execution by a processor based upon history data associated with such instructions. In particular, the history data for a given instruction identifies the next instruction that was executed immediately subsequent to the given instruction. An instruction history cache is utilized in some implementations to store history data representing predicted next instructions for a plurality of instructions stored in a memory, and the instruction history cache is operated concurrently with a secondary instruction cache so that predicted and actual next instructions may be retrieved in parallel. Predicted next instructions are speculatively executed when retrieved from the instruction history cache; however, execution of such instructions is terminated if the predicted and actual next instructions do not match. Also, in some implementations, the history data in the instruction history cache that is associated with a particular instruction may represent a predicted instruction to execute at least two cycles subsequent to execution of that particular instruction. In other implementations, history data for use in predicting next instructions may be embedded within instructions themselves, often eliminating the need for a separate instruction history cache.
|
