| 摘要 |
PURPOSE: A level shifter is provided which minimizes overlap current that is generated when a low signal level is converted into a high signal level to reduce current consumption and improve operation speed. CONSTITUTION: A level shifter includes an inverter(INV0) for inverting an input signal, an NMOS transistor(MN0) whose gate accepts the output of the inverter and whose drain is connected to a node B, the first inverter(INV1) for inverting the output of the inverter, and the first NMOS transistor(MN1) whose gate receives the output of the first inverter and whose drain is connected to a node C. The level shifter further has a PMOS transistor(MP0) whose gate is connected to the node C and whose drain is connected to the node B, the third NMOS transistor(MN3) whose gate accepts the output of the first inverter and whose source is coupled to the node B, and the first PMOS transistor(MP1) whose gate is connected to the node B and whose drain is connected to the node C. The level shifter also includes the fourth NMOS transistor(MN4) whose gate receives the output of the inverter and whose source is connected to the node C, the second PMOS transistor(MP2) whose gate is connected to the node C and whose drain is connected to a node D, and the second NMOS transistor(MN2) whose gate is connected to the node C and whose drain is connected to the node D. An output signal is output from the node D.
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