RAMBUS DRAM SEMICONDUCTOR DEVICE REALIZING EXTENDED NAP STATE

摘要

PURPOSE: A RAMBUS DRAM semiconductor device realizing an extended NAP state is provided which is refreshed for a period of time requiring synchronization information of inner clock signals and external clock signals stored in capacitors when introduced into an NAP mode, to extend the function of NAP state. CONSTITUTION: A RAMBUS DRAM semiconductor device having a DRAM cell array, a logic interface and a delay locked loop providing multiple inner clock signals to the logic interface includes a duty cycle correcting unit(341), and a controller(321). The duty cycle correcting unit receives an external clock signal, corrects the duty cycle of the external clock signal to generate a duty cycle correction signal and provide the duty cycle correction signal to the inside of the delay locked loop. The duty cycle correcting unit includes a capacitor that maintains the NAP state for a predetermined period of time when the RAMBUS DRAM is introduced into the NAP state. The controller, connected to the duty cycle correcting unit, receives a refresh signal for refreshing the DRAM cell array, a refresh enable signal and external bit signals, and generates an amplification driving signal to refresh the capacitor at least once within a predetermined period of time to keep the NAP mode maintenance time longer than the predetermined period of time.