发明名称 SEMICONDUCTOR CHIP PACKAGE HAVING MULTILAYERED LEAD
摘要 PURPOSE: A semiconductor chip package having a multilayered lead is provided to minimize the size of the package to a chip-size level and to reduce a coupling resistance as well as a resistance component of the lead. CONSTITUTION: The package includes a semiconductor chip(30) having a plurality of contact pads, bonding wires(34), a double-sided adhesive tape(36), lower and upper leads(39,43), and a mold housing(48). The lower and upper leads(39,43) are composed of inner leads(38,42) and outer leads(40,44), respectively. The inner leads(38) of the lower leads(39) are attached to the chip(30) by the adhesive tape(36) and electrically connected to the contact pads by the bonding wires(34). Additionally, the inner leads(42) of the upper leads(43) are disposed above the inner leads(38) of the lower leads(39) and electrically connected to the corresponding contact pads by another bonding wires(34) while an insulating substance(46) such as polyimide is interposed between the lower and upper leads(39,43) but exposing a bonding region on the lower leads(39) for the bonding wires(34). The outer leads(40,44) out of the mold housing(48) are arranged in the same plane.
申请公布号 KR20010036142(A) 申请公布日期 2001.05.07
申请号 KR19990043015 申请日期 1999.10.06
申请人 SAMSUNG ELECTRONICS CO., LTD. 发明人 KIM, JAE HUN
分类号 H01L23/12;H01L23/495 主分类号 H01L23/12
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