FREQUENCY MULTIPLIER USING DELAY LINES

摘要

PURPOSE: A frequency multiplier using delay lines is provided to generate double video clocks synchronized precisely using a simple CMOS logic. CONSTITUTION: In a frequency multiplier, the first delay line(503) inputs a system clock pulse and delays clock pulses respectively by serial-connected n numbers of gate delays. The second delay line(508) inputs synchronous signals and delays the signals respectively by serial-connected n numbers of gate delays. A latch(504) latches the output signals of the respective gate delays included in the first delay line depending on the desired periods. An encoder(505) analyzes logic values of values stored in the latch and generates a delay control value which digitizes a gate delay location corresponding to a desired duty. A multiplexer inputs the output signals of the respective gate delay included in the second delay line, and selects and outputs one input signal depending on the delay control value. An exclusive OR gate(509) performs an exclusive-OR operation of the synchronous signal and the output signal of the multiplexer.