发明名称 |
Sample and hold circuit for analog-digital converter, has voltage stabilizer connected to MOS transistor, which supplies specific potential to transistor |
摘要 |
The circuit has MOS transistor (3) and holding capacitor arranged between amplifiers (1,2). A voltage stabilizer (6) connected to MOS transistor, supplies stabilized voltage to transistor.
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申请公布号 |
DE10052939(A1) |
申请公布日期 |
2001.05.03 |
申请号 |
DE20001052939 |
申请日期 |
2000.10.25 |
申请人 |
AGILENT TECHNOLOGIES JAPAN, LTD. |
发明人 |
KAKITANI, HISAO |
分类号 |
G11C27/02;H03K17/00;H03M1/12;(IPC1-7):G11C27/02 |
主分类号 |
G11C27/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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