Design validation method for integrated system chip circuit, involves validating entire design using simulation test banks of complete system chip and execution of application

摘要

Interfaces between individual modules, chip internal buses of modules and connection logic are verified by simulation test banks designed by system chip development engineer and using user programmable gate array or emulation of logic. Time control of module at various critical path level is verified and entire design is validated by simulation test banks of complete system chip and application execution. An Independent claim is also included for integrated system chip circuit.