发明名称 |
Method and apparatus for reducing bleed currents within a DRAM array having row-to-column shorts |
摘要 |
A DRAM memory array is disclosed that uses a current limiting circuit employing current feedback to clamp the current flow to reduced levels than were previously possible. The current limiting circuit comprises a long length, depletion mode transistor that has its gate voltage reduced when row-to-column shorts exist to limit the bleed current. An alternative embodiment uses a P-channel FET in series with the depletion mode transistor and has its gate tied to a negative supply and passes current until both digit lines approach approximately 0.3 Volts.
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申请公布号 |
US6226221(B1) |
申请公布日期 |
2001.05.01 |
申请号 |
US20000521756 |
申请日期 |
2000.03.09 |
申请人 |
MICRON TECHNOLOGY, INC. |
发明人 |
MA MANNY KIN F.;SHIRLEY BRIAN |
分类号 |
G03G15/20;G11C11/4094;G11C29/02;G11C29/50;(IPC1-7):G11C8/00 |
主分类号 |
G03G15/20 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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