发明名称 |
Reference loop for a digital-to-analog converter |
摘要 |
An improved reference loop for a digital-to-analog converter (DAC) uses an approximate 50% duty cycle to improve the DC performance and the drift of the DAC at mid-scale. The 50% duty cycle also allows the DAC to provide the same performance over all outputs irrespective of the number of bits supplied to each input. The 50% duty cycle for the reference loop may be obtained from one of the DAC system outputs by forcing that output to supply a square wave output signal which may be used as input for the reference loop. The reference loop may alternatively be supplied by a DAC clock that is divided to obtain the desired 50% duty cycle input to the reference loop, in which case all outputs of the DAC are available for system output.
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申请公布号 |
US6225930(B1) |
申请公布日期 |
2001.05.01 |
申请号 |
US19990314090 |
申请日期 |
1999.05.18 |
申请人 |
AGILENT TECHNOLOGIES, INC. |
发明人 |
FELPS JIMMIE D |
分类号 |
H03M1/82;H03M1/06;H03M1/10;H03M1/66;(IPC1-7):H03M1/66 |
主分类号 |
H03M1/82 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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