| 摘要 |
A method of testing an integrated circuit having core logic with two or more clock domains and at least one signal path originating in one clock domain a nd terminating in an other clock domain, each signal path having a source contr ol element in the one clock domain and an associated destination control elemen t inthe other clock domain, each the control element bei ng a scannable memory element, the method comprising the steps of, for each the control element sh ifting a test stimulus into all scannable elements in the core logic; placing an asso ciated source control element in a hold mode for a predetermined number of clock cy clesprior to a capture operation so that the source cont rol element holds its outputconstant during the predetermined number of cloc k cycles; performing a capture operation for capturing the data output in response to the test stimulus by the control element and by all other scannable elements which are not control elements; maintaining an associated source control element in a hold mode for a predetermined number of clock cycles following a capture operation so that t he source control element holds its output constant during the predetermined nu mber of clock cycles; shifting out data captured in the capturing step; and analyzin g the data captured in the capturing step. An integrated circuit for use with the metho d comprises a source control element and an associated destination control associated with each signal path for exchanging data between the one and the other of the clock domains, the source control element being located in the one cl ock domain and the associated destination element being located in the other dom ain;each control element being a scannable memory elemen t having an input and an output and being configurable a SHIFT mode for shifting data from its input to its output and a CAPTURE mode for capturing data applied its input, each the sou rce control element being further configurable in a HOLD mode for holding its ou tputconstant; and the control elements being configurabl e in the modes in response to predetermined combinations of a Scan Enable signal for enabling or disabling shifting of data therethrough and a Capture Disable signal having a one valu e tocause a recipient control element to enable the capt ure mode and another value to cause a recipient control element to suppress the capture mode.
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