| 摘要 |
In a digital demodulation apparatus, a first signal generating circuit generates a first clock signal and a first frame signal which are always in an active state, and a second signal generating circuit generates a second clock signal and a second frame signal which are intermittently in an active state. An analog-to-digital converter converts an intermediate analog signal into a digital signal. A smoothing digital filter performs a smoothing operation upon the digital signal in synchronization with the first clock signal and the first frame signal to general parallel data. A data phase synchronization circuit converts the parallel data into serial data in synchronization with the second clock signal and the second frame signal. A digital signal processing circuit performs a signal processing operation upon the serial data in synchronization with the second clock signal and the second frame signal.
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