| 摘要 |
A process for forming high quality gate silicon dioxide layers of multiple thicknesses. The process includes steps of first providing a semiconductor substrate (e.g., a silicon wafer) with at least a first active area, a second active area and an electrical isolation region separating the first and second active area, followed by the formation of a first gate silicon dioxide layer of a predetermined thickness (typically less than 100 angstroms) on the first and second active areas. A first silicon layer (e.g., a polysilicon or amorphous silicon layer) is then deposited on the first gate silicon dioxide layer and the electrical isolation region. Next, the first silicon layer is patterned using, for example, photolithographic and etching techniques, to form a patterned first silicon layer and to expose a portion of the first gate silicon dioxide layer that was grown on the second active area. Next, the exposed portion of the first gate silicon dioxide layer is removed and a second gate silicon dioxide layer of another predetermined thickness is formed on the second active area. A second silicon layer (e.g., a polysilicon or amorphous silicon layer) is then deposited on the second gate silicon dioxide layer and overlying the patterned first silicon layer. Finally, the second silicon layer is patterned to form a patterned second silicon layer.
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