发明名称 ARITHMETIC PROCESSOR AND ARITHMETIC PROCESSING METHOD
摘要 PROBLEM TO BE SOLVED: To reduce the power consumption of a convolution encoding processing and to improve the speed of the processing. SOLUTION: An AND circuit 104 fixes output to '0' when the value of a register 6 is '0' and outputs the value of a shift register 4 as it is when the value of the register 6 is '1'. An AND circuit 105 fixes output to '0' when the value of the register 6 is '0'. The AND circuit 105 outputs the value of a selector 12 as it is in the case of an initial stage when the value of the register 6 is '1' and outputs the value of a selector 102 in (i-1)-th stage is outputted as it is in the case except for the initial stage.
申请公布号 JP2001119307(A) 申请公布日期 2001.04.27
申请号 JP19990294816 申请日期 1999.10.18
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 ISHIKAWA TOSHIHIRO
分类号 G06F11/10;H03M13/13;H03M13/23;H03M13/27;H03M13/29;(IPC1-7):H03M13/23 主分类号 G06F11/10
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