| 摘要 |
PROBLEM TO BE SOLVED: To decrease a bit width of synchronous parallel patterns outputted from a synchronous position detector. SOLUTION: A synchronous position detector where the synchronous parallel patterns generated in succeeding serial-parallel conversion is classified into 1st and 2nd groups in response to reception timing of a synchronous serial signal and the execution timing of first serial-parallel conversion, is provided with a combination logic means that converts a synchronous parallel pattern whose position identification bit and attribute identification bit are both active and a synchronous parallel pattern whose position identification bit only is active in the inside of the 1st and 2nd groups respectively and between the 1st and 2nd groups into one synchronous parallel pattern with a smaller bit width on the condition that the position identification bit and the attributed identification bit of the synchronous parallel pattern have a prescribed position relation. |
