TIMING VERIFICATION METHOD AND STORAGE MEDIUM STORING TIMING VERIFICATION PROGRAM

摘要

PROBLEM TO BE SOLVED: To easily and exactly verify timing in a short time concerning a semiconductor device provided with a PLL or DLL. SOLUTION: Concerning this timing verification method, when a PLL circuit exists on a clock path formed between a clock supply terminal for supplying a first clock designated as a verification object and the clock input terminal of an FF set at the terminal as a verification object, a second terminal clock delay value is found on the basis of a first terminal clock delay value DCE1, the jitter of the PLL and an stationary phase error.