Digital logic circuit fault analysis method, creating history of states by cyclically checking internal circuit nodes while inputting standard signals and retracing when halted due to error

摘要

The method involves applying input signals to the circuit under test and establishing the necessary protocol, then cyclically reading the switching states of the internal circuit nodes via the associated image registers. The states are stored for each cycle to generate a historical record which can be retraced in the event of a fault, when the operation of the logic circuit is forcibly halted. At the same time a program simulation is performed using the protocol-formatted input signals and the switching states stored for the cycle which has been returned to. An Independent claim is included for a device for analyzing faults in digital logic circuits.