发明名称 PLL CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a PLL circuit which prevents the occurrence of a phase offset and reduces an operation voltage. SOLUTION: A phase control part 21 of the PLL circuit where a charge pump part is divided into two of an integrating part 20 and the phase control part 21 outputs differential outputs, and two outputs are connected by a resistance element R to eliminate a bias difference, and thus a stable low-voltage operation is realized.
申请公布号 JP2001119296(A) 申请公布日期 2001.04.27
申请号 JP19990296376 申请日期 1999.10.19
申请人 NEC CORP 发明人 TANIMOTO SUSUMU
分类号 H03L7/093;H03L7/08;H03L7/085;H03L7/089;H03L7/18 主分类号 H03L7/093
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