BIT PHASE SYNCHRONIZING CIRCUIT

摘要

PROBLEM TO BE SOLVED: To surely perform capturing and reproducing of input data even when the distortion phase fluctuation of bit width occurs. SOLUTION: This circuit is provided with a toggle data generating circuit 1 for generating toggle data Tg1 and Tg2 with the rising and falling edges of input data Din containing a fixed pattern used as triggers, sampling circuit 2 for generating sampling data groups Tg1-S(n) and Tg2-S (n) by latching these toggle data Tg1 and Tg2 with a multi-phase clock CLK(n) of n (n>=2) phases, data selecting circuit 3 for selecting sampling data Tg1-A and Tg2-A away from the sampling data, with which a change point is first detected, for three or four phases, elastic circuit 4 for changing these data from the multi-phase clock to a clock CKI, and data reproducing circuit for relocating data, detecting the fixed pattern contained in the input data Din and fixing a phase thereof.