发明名称 |
Phase-locked loop or delay-locked loop circuitry for programmable logic devices |
摘要 |
A programmable logic device is provided with phase-locked loop ("PLL") or delay-locked loop ("DLL" ) circuitry in which the feedback loop circuitry substantially parallels and duplicates a portion of the clock signal distribution network on the device that receives the main PLL/DLL output signal. In this way the distributed feedback loop circuit more readily provides a substantially exact match for the distributed delay experienced by the signal propagating through the clock signal distribution network that the PLL/DLL circuitry serves.
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申请公布号 |
US2001000426(A1) |
申请公布日期 |
2001.04.26 |
申请号 |
US20000736065 |
申请日期 |
2000.12.13 |
申请人 |
ALTERA CORPORATION |
发明人 |
SUNG CHIAKANG;HUANG JOSEPH;WANG BONNIE I.;BIELBY ROBERT R.N. |
分类号 |
G06F1/10;H03L7/081;H03L7/099;(IPC1-7):G06F1/04;G06F1/06;H03L7/06 |
主分类号 |
G06F1/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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