Semiconductor memory device with reduced power consumption and stable operation in data holding state

摘要

The semiconductor memory device has a normal operation mode and a self-refresh mode, and includes a VBB generation circuit generating a first substrate voltage when an internal power supply voltage is larger than a predetermined value and a second substrate voltage of an absolute value smaller than that of the first substrate voltage when VCC is smaller than the predetermined value, a bit line equivalent voltage generation circuit outputting voltage VCC/2 produced by resistive dividing when internal power supply voltage is lower than the predetermined value in self-refresh mode, a 4KE signal generation circuit generating a signal for performing a 4K operation in the self-refresh mode when internal power supply voltage is lower than the predetermined value and a refresh address generation circuit.