发明名称 Procedure for identification of integrated circuit by generation of faulty or erroneous memory cells within memory and identification of the circuit from the faulty memory cell pattern, with no need to hard-wire a serial number
摘要 Identification of an integrated circuit is using a number of erroneous memory cells (7, 8, 9) that are produced during manufacture as an identifying pattern and from which a circuit identification number is produced.
申请公布号 DE19951048(A1) 申请公布日期 2001.04.26
申请号 DE1999151048 申请日期 1999.10.22
申请人 INFINEON TECHNOLOGIES AG 发明人 HARTMANN, RALF
分类号 G11C5/00;G11C16/20;G11C29/04;G11C29/44;H01L23/544;(IPC1-7):G11C29/00;G06F12/14 主分类号 G11C5/00
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