| 摘要 |
<p>A circuit arrangement (10, 110) and method for testing the differential non-linearity (DNL) of a digital-to-analog converter (DAC) (20, 120) determines whether the digital-to-analog converter has an analog output (22, 122) that is monotonic, and thus the DAC is functional. The design is appropriate for being implemented on an integrated circuit containing a digital-to-analog converter, creating an efficient self-test circuit arrangement. A counter (12, 112) generates a monotonic sequence of digital input codes for a digital input of the digital-to-analog converter. A monotonicity comparator (24, 24', 24'', 124), such as a one-stage or multistage sample and hold circuit arrangement, detects any non-monotonic transition in the analog output of the digital-to-analog converter, generating an error signal as an output. An output switch, such as a digital flip-flop (37', 37'', 137), may be set by the error signal, for monitoring by other devices. A clock signal synchronizes the counter and the monotonicity comparator. A reset signal may be included to reset the counter to the first digital input code in the sequence. The reset may also reset the output switch.</p> |
