| 摘要 |
A memory system is provided that controls a memory that must be refreshed, such as DRAM, in a manner that does not require extensive external control. In one embodiment, the memory system includes a memory controller and a memory block that are coupled by a system bus. The memory block includes an array of memory cells that must be periodically refreshed to maintain valid data. The memory block also includes a refresh control circuit that refreshes the memory cells during idle cycles of the memory array. The memory controller monitors the number of idle cycles on the system bus during a predetermined refresh period. If the number of monitored idle cycles is less than a predetermined required number of idle cycles, the memory controller forces the required number of idle cycles on the system bus. As a result, the memory controller ensures that there will always be enough idle cycles in which the memory array can be refreshed.
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