发明名称 System and method for interfacing an input/output system memory to a host computer system memory
摘要 A system and method for interfacing between an input/output system, that includes a local computer bus, a processor connected to the local computer bus and an interface to a computer system bus, and a computer system having a main memory is provided. The system includes a memory system with a memory controller that controls access and storage of data. The system may initiate sequential or burst ordered blocks of data over the computer bus from the computer system in anticipation of random access requests for data by the processor. A system and method for interfacing a plurality of processors to a computer system having a system bus and a main memory is also provided.
申请公布号 US6223266(B1) 申请公布日期 2001.04.24
申请号 US19970914960 申请日期 1997.08.20
申请人 CYPRESS SEMICONDUCTOR CORP. 发明人 SARTORE RONALD H.
分类号 G06F12/08;(IPC1-7):G06F12/00;G06F13/00;G06F13/38;G06F13/40 主分类号 G06F12/08
代理机构 代理人
主权项
地址