Apparatus and method for reducing defects in a semiconductor lithographic process

摘要

An arrangement for optimizing a lithographic process forms a pattern on a silicon wafer using a photocluster cell system to simulate an actual processing condition for a semiconductor product. The resist pattern is then inspected using a wafer inspection system. An in-line low voltage scanning electron microscope (SEM) system reviews and classifies defect types, enabling generation of an alternative processing specification. The alternative processing specification can then be tested by forming patterns on different wafers, and then performing split-series testing to analyze the patterns on the different wafers for comparison with the existing lithographic process and qualification for production.